********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Mar 09, 2015
*ECN S15-0445, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR606DP D G S 
M1 3 GX S S NMOS W= 2305740u L= 0.3u 
M2 S GX S D PMOS W= 2305740u L= 0.27u 
R1 D 3 1.229e-02 6.298e-03 1.854e-05 
CGS GX S 8.956e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 9.080e-04 -6.366e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2305740u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.065e-05 NSUB = 2.326e+17 
+ KAPPA = 8.000e-03 NFS = 4.477e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12  ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.436e+16 IS = 0 TPG = -1 CAPOP = 12  ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 9.920e-09 TREF = 25 BV = 101 
+RS = 4.906e-03 N = 1.114e+00 IS = 2.713e-12 
+EG = 1.237e+00 XTI = 3.189e-01 TRS = 2.455e-03 
+CJO = 5.236e-10 VJ = 1.546e+01 M = 7.555e-01 ) 
.ENDS 
